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» Reversible Fault-Tolerant Logic
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LOPSTR
1997
Springer
13 years 11 months ago
Implicit Program Synthesis by a Reversible Metainterpreter
Synthesis of logic programs is considered as a special instance of logic programming. We describe experience made within a logical metaprogramming environment whose central compone...
Henning Christiansen
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
14 years 1 months ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
14 years 1 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
PADS
2006
ACM
14 years 21 days ago
Aurora: An Approach to High Throughput Parallel Simulation
A master/worker paradigm for executing large-scale parallel discrete event simulation programs over networkenabled computational resources is proposed and evaluated. In contrast t...
Alfred Park, Richard M. Fujimoto
FPGA
2005
ACM
105views FPGA» more  FPGA 2005»
14 years 8 days ago
Soft error rate estimation and mitigation for SRAM-based FPGAs
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
Ghazanfar Asadi, Mehdi Baradaran Tahoori