As device scales shrink, higher transistor counts are available while soft-errors, even in logic, become a major concern. A new class of architectures, such as Merrimac and the IB...
Mattan Erez, Nuwan Jayasena, Timothy J. Knight, Wi...
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
PC grids represent massive computation capacity at a low cost, but are challenging to employ for parallel computing because of variable and unpredictable performance and availabili...
Nagarajan Kanna, Jaspal Subhlok, Edgar Gabriel, Es...
BPEL is the de facto standard for business process modeling in today's enterprises and is a promising candidate for the integration of business and scientific applications tha...
This poster paper summarizes our research on fault tolerance arising as a by-product of the evolutionary computation process. Past research has shown evidence of robustness emergin...