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» Rewriting-Based Techniques for Runtime Verification
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RTAS
2008
IEEE
14 years 4 months ago
Incorporating Resource Safety Verification to Executable Model-based Development for Embedded Systems
This paper formulates and illustrates the integration of resource safety verification into a design methodology for development of verified and robust real-time embedded systems. ...
Jianliang Yi, Honguk Woo, James C. Browne, Aloysiu...
TVLSI
2002
130views more  TVLSI 2002»
13 years 9 months ago
Incremental compilation for parallel logic verification systems
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...
R. Tessier, S. Jana
FPL
2000
Springer
128views Hardware» more  FPL 2000»
14 years 1 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght
TSE
2008
236views more  TSE 2008»
13 years 9 months ago
Provable Protection against Web Application Vulnerabilities Related to Session Data Dependencies
Web applications are widely adopted and their correct functioning is mission critical for many businesses. At the same time, Web applications tend to be error prone and implementat...
Lieven Desmet, Pierre Verbaeten, Wouter Joosen, Fr...
ASE
2010
129views more  ASE 2010»
13 years 10 months ago
Efficient monitoring of parametric context-free patterns
Recent developments in runtime verification and monitoring show that parametric regular and temporal logic specifications can be efficiently monitored against large programs. Howev...
Patrick O'Neil Meredith, Dongyun Jin, Feng Chen, G...