Incremental compilation for parallel logic verification systems

Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the overall ASIC verification flow. In this paper, we describe and analyze a set of incremental compilation steps that can be directly applied to a range of parallel logic verification hardware, including logic emulators. Important aspects of this work include the formulation and analysis of two incremental design mapping steps: the partitioning of newly added design logic onto multiple logic processors and the communication scheduling of newly added design signals between logic processors. To validate our incremental compilation techniques, the developed mapping heuristics have been integrated into the compilation flow for a field-programmable gate-array-based Ikos VirtuaLogic emulator [1]. The modified compiler has been applied to five large benchmark circuits that have been synthesized from register-transfer ...

• Type: Journal
• Year: 2002
• Where: TVLSI
• Authors: R. Tessier, S. Jana
• Keywords: Complete Design Recompilation, Incremental Compilation, Logic, TVLSI 2002