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DATE
2007
IEEE
126views Hardware» more  DATE 2007»
14 years 3 months ago
WAVSTAN: waveform based variational static timing analysis
— We present a waveform based variational static timing analysis methodology. It is a timing paradigm that lies midway between convention static delay approximations and full dyn...
Saurabh K. Tiwary, Joel R. Phillips
FPT
2005
IEEE
131views Hardware» more  FPT 2005»
14 years 2 months ago
Dynamic Voltage Scaling for Commercial FPGAs
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, ...
ICES
2001
Springer
91views Hardware» more  ICES 2001»
14 years 1 months ago
Untidy Evolution: Evolving Messy Gates for Fault Tolerance
Abstract. The exploitation of the physical characteristics has already been demonstrated in the intrinsic evolution of electronic circuits. This paper is an initial attempt at crea...
Julian F. Miller, Morten Hartmann
LREC
2008
115views Education» more  LREC 2008»
13 years 10 months ago
Evaluating Robustness Of A QA System Through A Corpus Of Real-Life Questions
This paper presents the sequential evaluation of the question answering system SQuaLIA. This system is based on the same sequential process as most statistical question answering ...
Laurianne Sitbon, Patrice Bellot, Philippe Blache
IOLTS
2009
IEEE
174views Hardware» more  IOLTS 2009»
14 years 3 months ago
ATPG-based grading of strong fault-secureness
—Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considere...
Marc Hunger, Sybille Hellebrand, Alejandro Czutro,...