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    » Robustness of Temporal Logic Specifications
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    DLOG
    2006
    143views Automated Reasoning» more  DLOG 2006»
    Model checking the basic modalities of CTL with Description Logic
    13 years 9 months ago
    Model checking the basic modalities of CTL with Description Logic
    Download  ftp.informatik.rwth-aachen.de
    Abstract. Model checking is a fully automated technique for determining whether the behaviour of a finite-state reactive system satisfies a temporal logic specification. Despite th...
    Shoham Ben-David, Richard J. Trefler, Grant E. Wed...
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    LREC
    2010
    187views Education» more  LREC 2010»
    Analysing Temporally Annotated Corpora with CAVaT
    13 years 9 months ago
    Analysing Temporally Annotated Corpora with CAVaT
    Download  www.lrec-conf.org
    We present CAVaT, a tool that performs Corpus Analysis and Validation for TimeML. CAVaT is an open source, modular checking utility for statistical analysis of features specific t...
    Leon Derczynski, Robert J. Gaizauskas
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    PSTV
    1993
    123views Hardware» more  PSTV 1993»
    On the Verification of Temporal Properties
    13 years 9 months ago
    On the Verification of Temporal Properties
    Download  spinroot.com
    We present a new algorithm that can be used for solving the model−checking problem for linear−time temporal logic. This algorithm can be viewed as the combination of two exist...
    Patrice Godefroid, Gerard J. Holzmann
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    ENTCS
    2006
    114views more  ENTCS 2006»
    Run-Time Checking of Dynamic Properties
    13 years 7 months ago
    Run-Time Checking of Dynamic Properties
    Download  react.cs.uni-sb.de
    We consider a first-order property specification language for run-time monitoring of dynamic systems. The language is based on a linear-time temporal logic and offers two kinds of...
    Oleg Sokolsky, Usa Sammapun, Insup Lee, Jesung Kim
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    DAC
    2006
    ACM
    96views Computer Architecture» more  DAC 2006»
    Rapid estimation of control delay from high-level specifications
    14 years 8 months ago
    Rapid estimation of control delay from high-level specifications
    Download  web.ics.purdue.edu
    We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
    Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
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