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» Route Packets, Not Wires: On-Chip Interconnection Networks
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SLIP
2003
ACM
14 years 1 months ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
ISCA
2007
IEEE
111views Hardware» more  ISCA 2007»
14 years 2 months ago
Express virtual channels: towards the ideal interconnection fabric
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Nira...
ANCS
2008
ACM
13 years 10 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
INFOCOM
1997
IEEE
14 years 25 days ago
Performance of Multicasting Closed Interconnection Networks
This paper examines the application of a simple yet general packet replication scheme to achieve multicasting in closed interconnection networks. The performance of these networks...
Cathy W. Chan, Soung C. Liew
MOBICOM
2009
ACM
14 years 3 months ago
A scalable micro wireless interconnect structure for CMPs
This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to inte...
Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, So...