116 search results - page 15 / 24 » Route Packets, Not Wires: On-Chip Interconnection Networks |
MICRO
2009
IEEE
14 years 3 months ago
2009
IEEE
As technology scaling drives the number of processor cores upward, current on-chip routers consume substantial portions of chip area and power budgets. Since existing research has...
FPL
2005
Springer
14 years 2 months ago
2005
Springer
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
TC
2008
13 years 8 months ago
2008
Component failures and planned component replacements cause changes in the topology and routing paths supplied by the interconnection network of a parallel processor system over ti...
CCGRID
2001
IEEE
14 years 7 days ago
2001
IEEE
This paper describes the principles of an original adaptive interconnect for a computational cluster. Torus topology (2d or 3d) is used as a basis but nodes are allowed to effecti...
ICNP
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract— Despite years of research and development, pioneering deployments of multihop wireless networks have not proven successful. The performance of routing and transport is ...