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» Router designs for elastic buffer on-chip networks
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ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
14 years 1 months ago
The design and implementation of a low-latency on-chip network
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
Robert D. Mullins, Andrew West, Simon W. Moore
ICDCS
2005
IEEE
14 years 29 days ago
Network-Centric Buffer Cache Organization
A pass-through server such as an NFS server backed by an iSCSI[1] storage server only passes data between the storage server and NFS clients. Ideally it should require at most one...
Gang Peng, Srikant Sharma, Tzi-cker Chiueh
SIPS
2007
IEEE
14 years 1 months ago
Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency
System-on-Chip (SoC) designs become more complex nowadays. The communication between each processing element often suffers challenges due to the wiring problem. Networks-on-Chip (...
Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu
ACSAC
2004
IEEE
13 years 11 months ago
CTCP: A Transparent Centralized TCP/IP Architecture for Network Security
Many network security problems can be solved in a centralized TCP (CTCP) architecture, in which an organization's edge router transparently proxies every TCP connection betwe...
Fu-Hau Hsu, Tzi-cker Chiueh
AINA
2010
IEEE
13 years 4 months ago
TCP Testing: How Well Does ns2 Match Reality?
New transport protocols continue to appear as alternatives to the Transmission Control Protocol (TCP). Many of these are are designed to address TCP's inefficiency in operatin...
Martin Bateman, Saleem N. Bhatti