Sciweavers

78 search results - page 13 / 16
» Router designs for elastic buffer on-chip networks
Sort
View
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
14 years 2 months ago
Latency criticality aware on-chip communication
—Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip da...
Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe S...
NETWORKING
2010
13 years 8 months ago
Stateless RD Network Services
Rate-Delay (RD) Network Services constitute a promising differentiated-services architecture for multi-provider networks, by offering users a choice between high throughput or low ...
Maxim Podlesny, Sergey Gorinsky
NOCS
2008
IEEE
14 years 1 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
TVLSI
2008
157views more  TVLSI 2008»
13 years 7 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung
NOCS
2008
IEEE
14 years 1 months ago
Reducing the Interconnection Network Cost of Chip Multiprocessors
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
Pablo Abad, Valentin Puente, José-Án...