78 search results - page 8 / 16 » Router designs for elastic buffer on-chip networks |
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
MASCOTS
2004
13 years 8 months ago
2004
Architectural designs for routers and networks of routers to support mobile communication are analysed for their end-to-end performance using a simple Markov model. In view of the...
DAC
2009
ACM
14 years 1 days ago
2009
ACM
Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
INFOCOM
2007
IEEE
14 years 1 months ago
2007
IEEE
— There is growing interest in designing high speed routers with small buffers that store only tens of packets. Recent studies suggest that TCP NewReno, with the addition of a pa...