Sciweavers

55 search results - page 9 / 11
» Run-time compaction of FPGA designs
Sort
View
SUTC
2010
IEEE
13 years 5 months ago
Hardware Implementation of Symbol Synchronization for Underwater FSK
—— Symbol synchronization is a critical component in the design of an underwater acoustic modem. Without accurate symbol synchronization, higher bit error rates incur thus reduc...
Ying Li, Xing Zhang, Bridget Benson, Ryan Kastner
FPL
2008
Springer
138views Hardware» more  FPL 2008»
13 years 9 months ago
An efficient run-time router for connecting modules in FPGAS
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents ...
Jorge Surís, Cameron Patterson, Peter Athan...
FPGA
2006
ACM
90views FPGA» more  FPGA 2006»
13 years 11 months ago
Improving performance and robustness of domain-specific CPLDs
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
Mark Holland, Scott Hauck
EGPGV
2004
Springer
181views Visualization» more  EGPGV 2004»
14 years 24 days ago
Parallel Multiresolution Volume Rendering of Large Data Sets with Error-Guided Load Balancing
We present a new parallel multiresolution volume rendering algorithm for visualizing large data sets. Using the wavelet transform, the raw data is first converted into a multires...
Chaoli Wang, Jinzhu Gao, Han-Wei Shen
IPSN
2004
Springer
14 years 23 days ago
Sensing uncertainty reduction using low complexity actuation
The performance of a sensor network may be best judged by the quality of application specific information return. The actual sensing performance of a deployed sensor network depe...
Aman Kansal, Eric Yuen, William J. Kaiser, Gregory...