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» Runtime Support for Multicore Packet Processing Systems
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FPGA
2001
ACM
162views FPGA» more  FPGA 2001»
15 years 7 months ago
Reprogrammable network packet processing on the field programmable port extender (FPX)
A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extend...
John W. Lockwood, Naji Naufel, Jonathan S. Turner,...
CF
2008
ACM
15 years 4 months ago
DMA-based prefetching for i/o-intensive workloads on the cell architecture
Recent advent of the asymmetric multi-core processors such as Cell Broadband Engine (Cell/BE) has popularized the use of heterogeneous architectures. A growing body of research is...
M. Mustafa Rafique, Ali Raza Butt, Dimitrios S. Ni...
VSTTE
2005
Springer
15 years 8 months ago
Performance Validation on Multicore Mobile Devices
The validation of modern software systems on mobile devices needs to incorporate both functional and non-functional requirements. While some progress has been made in validating pe...
Thomas Hubbard, Raimondas Lencevicius, Edu Metz, G...
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POPL
2012
ACM
13 years 10 months ago
A compiler and run-time system for network programming languages
Software-defined networks (SDNs) are a new implementation architecture in which a controller machine manages a distributed collection of switches, by instructing them to install ...
Christopher Monsanto, Nate Foster, Rob Harrison, D...
IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
14 years 5 months ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross