252 search results - page 33 / 51 » Runtime Verification Using a Temporal Description Logic |
FOAL
2009
ACM
13 years 11 months ago
2009
ACM
In this paper we specify an operational run-time semantics of Assignment Featherweight Java -- a minimal subset of Java with assignments -- with around advice, using graph transfo...
EJWCN
2010
13 years 2 months ago
2010
Model checking (MC) is a formal verification technique which has known and still knows a resounding success in the computer science community. Realizing that the distributed power...
RE
2001
Springer
14 years 7 days ago
2001
Springer
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
the interconnection among the IP cores with all description levels This paper presents an automatic interconnection rectification (AIR)technique to correct the misplaced interconne...