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ICPP
2003
IEEE
14 years 1 months ago
Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
Christos D. Antonopoulos, Dimitrios S. Nikolopoulo...
FTCS
1998
77views more  FTCS 1998»
13 years 9 months ago
Strong Partitioning Protocol for a Multiprocessor VME System
The trend in implementing today's embedded applications is toward the use of commercial-off-the-shelf open architecture. Reducing costs and facilitating systems integration a...
Mohamed F. Younis, Jeffrey X. Zhou, Mohamed Abouta...
SOSP
1993
ACM
13 years 9 months ago
The Information Bus - An Architecture for Extensible Distributed Systems
Research can rarely be performed on large-scale, distributed systems at the level of thousands of workstations. In this paper, we describe the motivating constraints, design princ...
Brian M. Oki, Manfred Pflügl, Alex Siegel, Da...
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler
DAC
1997
ACM
14 years 3 days ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling