103 search results - page 6 / 21 » SEU tolerant device, circuit and processor design |
CAMP
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— The promise of next-generation computer technologies, such as nano-electronics, implies a number of serious alterations to the design flow of digital circuits. One of ...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
- The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical fra...
DSD
2007
IEEE
13 years 11 months ago
2007
IEEE
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
ICES
2005
Springer
14 years 28 days ago
2005
Springer
This paper describes circuit evolutionary experiments at extreme low temperatures, including the test of all system components at this extreme environment (EE). In addition to hard...
CASES
2011
ACM
12 years 7 months ago
2011
ACM
Escalating variations in modern CMOS designs have become a threat to Moore’s law. While previous works have proposed techniques for tolerating variations by trading reliability ...