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WCET
2010
13 years 5 months ago
A Code Policy Guaranteeing Fully Automated Path Analysis
Calculating the worst-case execution time (WCET) of real-time tasks is still a tedious job. Programmers are required to provide additional information on the program flow, analyzi...
Benedikt Huber, Peter P. Puschner
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 1 months ago
On Statistical Timing Analysis with Inter- and Intra-Die Variations
In this paper, we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a numb...
Hratch Mangassarian, Mohab Anis
TR
2008
67views more  TR 2008»
13 years 7 months ago
Degradation Analysis of Nano-Contamination in Plasma Display Panels
Abstract--As an alternative to traditional life testing, degradation tests can be effective in assessing product reliability when measurements of degradation leading to failure can...
Suk Joo Bae, Seong-Joon Kim, Man Soo Kim, Bae Jin ...
SOFSEM
1997
Springer
13 years 12 months ago
Path Layout in ATM Networks
This paper surveys recent results in the area of virtual path layout in ATM networks. We present a model for the theoretical study of these layouts the model amounts to covering t...
Shmuel Zaks
PLDI
2005
ACM
14 years 1 months ago
Path slicing
We present a new technique, path slicing, that takes as input a possibly infeasible path to a target location, and eliminates all the operations that are irrelevant towards the re...
Ranjit Jhala, Rupak Majumdar