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FPGA
2009
ACM
201views FPGA» more  FPGA 2009»
14 years 2 months ago
A high-performance FPGA architecture for restricted boltzmann machines
Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of...
Daniel L. Ly, Paul Chow
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
14 years 2 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
IJCNN
2006
IEEE
14 years 2 months ago
A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering
— We describe an implementation of Gabor-type filters on field programmable gate arrays using the cellular neural network (CNN) architecture. The CNN template depends upon the ...
Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K....
COMCOM
2006
154views more  COMCOM 2006»
13 years 8 months ago
Wireless sensor networks for personal health monitoring: Issues and an implementation
Recent technological advances in sensors, low-power integrated circuits, and wireless communications have enabled the design of lowcost, miniature, lightweight, and intelligent ph...
Aleksandar Milenkovic, Chris Otto, Emil Jovanov
SC
2009
ACM
14 years 2 months ago
Allocator implementations for network-on-chip routers
The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we...
Daniel U. Becker, William J. Dally