Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...
In this paper, we describe a hybrid tool for hardware formal verification that links the HOL (higher-order logic) theorem prover and (multiway decision graphs) model checker. Our ...
Abstract. In this paper we describe the formal specification and verification of the efficient algorithm for real-time model checking implemented in the model checker RAVEN. It was...
This paper addresses the formal verification of diagnosis systems. We tackle the problem of diagnosability: given a partially observable dynamic system, and a diagnosis system obs...
Alessandro Cimatti, Charles Pecheur, Roberto Cavad...
IEEE 802.1x and authentication server based security protocols are mainly used for enhancing security of wireless networks. In this paper, we specify PAP and EAP-MD5 based securit...