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ARCS
2008
Springer
13 years 9 months ago
An Optimized ZGEMM Implementation for the Cell BE
: The architecture of the IBM Cell BE processor represents a new approach for designing CPUs. The fast execution of legacy software has to stand back in order to achieve very high ...
Timo Schneider, Torsten Hoefler, Simon Wunderlich,...
PVM
2010
Springer
13 years 5 months ago
Massively Parallel Finite Element Programming
Abstract. Today’s large finite element simulations require parallel algorithms to scale on clusters with thousands or tens of thousands of processor cores. We present data struc...
Timo Heister, Martin Kronbichler, Wolfgang Bangert...
ERSA
2006
111views Hardware» more  ERSA 2006»
13 years 8 months ago
Promises and Pitfalls of Reconfigurable Supercomputing
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
Maya Gokhale, Christopher Rickett, Justin L. Tripp...
LCPC
2005
Springer
14 years 27 days ago
Automatic Measurement of Instruction Cache Capacity
There is growing interest in autonomic computing systems that can optimize their own behavior on different platforms without manual intervention. Examples of successful self-opti...
Kamen Yotov, Sandra Jackson, Tyler Steele, Keshav ...
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
13 years 11 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...