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TC
2010
13 years 6 months ago
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
13 years 12 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
ANCS
2007
ACM
13 years 11 months ago
Frame-aggregated concurrent matching switch
Network operators need high-capacity router architectures that can offer scalability, provide throughput and performance guarantees, and maintain packet ordering. However, previou...
Bill Lin, Isaac Keslassy
NETWORK
2008
106views more  NETWORK 2008»
13 years 7 months ago
An Effective QoS Differentiation Scheme for Wireless Mesh Networks
Wireless mesh networking is emerging as an important architecture for future-generation wireless communications systems. Quality of service provisioning is a challenging issue in ...
Honglin Hu, Yan Zhang, Hsiao-Hwa Chen
DDECS
2008
IEEE
137views Hardware» more  DDECS 2008»
14 years 2 months ago
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
Zhonghai Lu, Lei Xia, Axel Jantsch