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ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
14 years 14 days ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...
SAMOS
2007
Springer
14 years 1 months ago
Online Prediction of Applications Cache Utility
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...
Miquel Moretó, Francisco J. Cazorla, Alex R...
ICDCS
1996
IEEE
13 years 11 months ago
Supporting a Flexible Parallel Programming Model on a Network of Workstations
We introduce a shared memory software prototype system for executing programs with nested parallelism on a network of workstations. This programming model exhibits a very convenie...
Shih-Chen Huang, Zvi M. Kedem
HPDC
2008
IEEE
14 years 1 months ago
Harmony: an execution model and runtime for heterogeneous many core systems
The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by ma...
Gregory F. Diamos, Sudhakar Yalamanchili
JSA
2007
162views more  JSA 2007»
13 years 7 months ago
Exploration of distributed shared memory architectures for NoC-based multiprocessors
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric inter...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...