Sciweavers

212 search results - page 38 / 43
» Scalable Hardware Architecture for Real-Time Dynamic Program...
Sort
View
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 5 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
PLDI
2011
ACM
12 years 10 months ago
EnerJ: approximate data types for safe and general low-power computation
Energy is increasingly a first-order concern in computer systems. Exploiting energy-accuracy trade-offs is an attractive choice in applications that can tolerate inaccuracies. Re...
Adrian Sampson, Werner Dietl, Emily Fortuna, Danus...
IEEEPACT
2007
IEEE
14 years 1 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick
PLDI
1994
ACM
13 years 11 months ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
CASES
2003
ACM
14 years 18 days ago
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main ...
Federico Angiolini, Luca Benini, Alberto Caprara