Sciweavers

212 search results - page 8 / 43
» Scalable Hardware Architecture for Real-Time Dynamic Program...
Sort
View
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
12 years 11 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
ACCV
2007
Springer
14 years 1 months ago
Task Scheduling in Large Camera Networks
Camera networks are increasingly being deployed for security. In most of these camera networks, video sequences are captured, transmitted and archived continuously from all cameras...
Ser-Nam Lim, Larry S. Davis, Anurag Mittal
CCS
2011
ACM
12 years 7 months ago
VMCrypt: modular software architecture for scalable secure computation
Garbled circuits play a key role in secure computation. Unlike previous work, which focused mainly on efficiency and automation aspects of secure computation, in this paper we foc...
Lior Malka
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 9 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
RTSS
2007
IEEE
14 years 1 months ago
Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts
In this paper, we propose to implement hybrid operating systems based on two-level hardware interrupts. To separate real-time and non-real-time hardware interrupts by hardware, we...
Miao Liu, Zili Shao, Meng Wang, Hongxing Wei, Tian...