2020 search results - page 12 / 404 » Scalable Instruction-Level Parallelism. |
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
MICRO
1994
IEEE
14 years 28 days ago
1994
IEEE
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...
MICRO
1994
IEEE
14 years 28 days ago
1994
IEEE
Branch instructions are recognized as a major impediment to exploiting instruction level parallelism. Even with sophisticated branch prediction techniques, many frequently execute...
WCET
2008
13 years 10 months ago
2008
WCET analysis models for superscalar out-of-order CPUs generally need to be pessimistic in order to account for a wide range of possible dynamic behavior. CPU hardware modificatio...
BIOCOMP
2006
13 years 10 months ago
2006
- Aligning specific sequences against other known sequences in a database is a central aspect of bioinformatics. New experimental data being added continuously to these databases n...