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RTCSA
2006
IEEE
14 years 4 months ago
Instruction Scheduling with Release Times and Deadlines on ILP Processors
ILP (Instruction Level Parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimisi...
Hui Wu, Joxan Jaffar, Jingling Xue
CF
2006
ACM
14 years 4 months ago
Kilo-instruction processors, runahead and prefetching
There is a continuous research effort devoted to overcome the memory wall problem. Prefetching is one of the most frequently used techniques. A prefetch mechanism anticipates the ...
Tanausú Ramírez, Alex Pajuelo, Olive...
VLDB
2005
ACM
180views Database» more  VLDB 2005»
14 years 3 months ago
Cache-conscious Frequent Pattern Mining on a Modern Processor
In this paper, we examine the performance of frequent pattern mining algorithms on a modern processor. A detailed performance study reveals that even the best frequent pattern min...
Amol Ghoting, Gregory Buehrer, Srinivasan Parthasa...
CGO
2003
IEEE
14 years 3 months ago
Phi-Predication for Light-Weight If-Conversion
Predicated execution can eliminate hard to predict branches and help to enable instruction level parallelism. Many current predication variants exist where the result update is co...
Weihaw Chuang, Brad Calder, Jeanne Ferrante
ISCA
1999
IEEE
105views Hardware» more  ISCA 1999»
14 years 2 months ago
The Program Decision Logic Approach to Predicated Execution
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
David I. August, John W. Sias, Jean-Michel Puiatti...