420 search results - page 83 / 84 » Scalable Parallel Programming with CUDA |
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
CCGRID
2006
IEEE
14 years 1 months ago
2006
IEEE
With the increasing number of processors in modern HPC(High Performance Computing) systems, there are two emergent problems to solve. One is scalability, the other is fault tolera...
IEEEPACT
2005
IEEE
14 years 28 days ago
2005
IEEE
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...