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» Scalable Test Generators for High-Speed Datapath Circuits
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HIPEAC
2011
Springer
12 years 7 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
ITC
2003
IEEE
197views Hardware» more  ITC 2003»
14 years 1 months ago
Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA)
A scalable laser-based timing analysis technique we call laser assisted device alteration (LADA) is introduced for the rapid isolation and analysis of defect-free performance limi...
Jeremy A. Rowlette, Travis M. Eiles