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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 24 days ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
CF
2011
ACM
12 years 7 months ago
Hybrid high-performance low-power and ultra-low energy reliable caches
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high vol...
Bojan Maric, Jaume Abella, Francisco J. Cazorla, M...
PODC
2009
ACM
14 years 4 months ago
Memory models: a case for rethinking parallel languages and hardware
The era of parallel computing for the masses is here, but writing correct parallel programs remains far more difficult than writing sequential programs. Aside from a few domains,...
Sarita V. Adve
CCS
2008
ACM
13 years 9 months ago
A fast real-time memory authentication protocol
We propose a new real-time authentication scheme for memory. As in previous proposals the scheme uses a Merkle tree to guarantee dynamic protection of memory. We use the universal...
Yin Hu, Ghaith Hammouri, Berk Sunar
JIPS
2008
112views more  JIPS 2008»
13 years 7 months ago
Two-Tier Storage DBMS for High-Performance Query Processing
: This paper describes the design and implementation of a two-tier DBMS for handling massive data and providing faster response time. In the present day, the main requirements of D...
Sang Hun Eo, Yan Li, Ho Seok Kim, Hae-Young Bae