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PACS
2004
Springer
115views Hardware» more  PACS 2004»
14 years 3 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
SENSYS
2003
ACM
14 years 3 months ago
Timing-sync protocol for sensor networks
Wireless ad-hoc sensor networks have emerged as an interesting and important research area in the last few years. The applications envisioned for such networks require collaborati...
Saurabh Ganeriwal, Ram Kumar, Mani B. Srivastava
AINA
2005
IEEE
14 years 3 months ago
3D-VOQ Switch Design and Evaluation
Input Buffered Switches with Virtual Output Queues(VOQ) design to avoid Head-Of-Line problems, is a primary design of switches that can be scalable to very high speeds. However, t...
Ding-Jyh Tsaur, Xian-Yang Lu, Chin-Chi Wu, Woei Li...
WSC
2004
13 years 11 months ago
A Framework for Adaptive Synchronization of Distributed Simulations
Increased complexity of simulation models and the related modeling needs for global supply chains have necessitated the execution of simulations on multiple processors. While dist...
Bertan Altuntas, Richard A. Wysk
IPPS
2003
IEEE
14 years 3 months ago
Optimizing Synchronization Operations for Remote Memory Communication Systems
Synchronization operations, such as fence and locking, are used in many parallel operations accessing shared memory. However, a process which is blocked waiting for a fence operat...
Darius Buntinas, Amina Saify, Dhabaleswar K. Panda...