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124
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ICS
2004
Tsinghua U.
15 years 9 months ago
Scaling the issue window with look-ahead latency prediction
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...
Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Gl...
IPPS
2010
IEEE
15 years 1 months ago
Using focused regression for accurate time-constrained scaling of scientific applications
Many large-scale clusters now have hundreds of thousands of processors, and processor counts will be over one million within a few years. Computational scientists must scale their ...
Bradley J. Barnes, Jeonifer Garren, David K. Lowen...
ICIP
2006
IEEE
16 years 5 months ago
Efficient 2-D Gray-Scale Dilations and Erosions with Arbitrary Flat Structuring Elements
An efficient algorithm is presented for the computation of gray-scale morphological operations with 2-D structuring elements (S.E.). The required computing time is independent of ...
Erik R. Urbach, Michael H. F. Wilkinson
154
Voted
CIKM
2008
Springer
15 years 5 months ago
Query suggestion using hitting time
Generating alternative queries, also known as query suggestion, has long been proved useful to help a user explore and express his information need. In many scenarios, such sugges...
Qiaozhu Mei, Dengyong Zhou, Kenneth Ward Church
128
Voted
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
15 years 9 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...