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DAC
2009
ACM
16 years 7 months ago
Context-sensitive timing analysis of Esterel programs
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abh...
IPPS
2007
IEEE
16 years 10 days ago
Distributed IDS using Reconfigurable Hardware
With the rapid growth of computer networks and network infrastructures and increased dependency on the internet to carry out day-to-day activities, it is imperative that the compo...
Ashok Kumar Tummala, Parimal Patel
NSDI
2008
15 years 8 months ago
Swift: A Fast Dynamic Packet Filter
This paper presents Swift, a packet filter for high performance packet capture on commercial off-the-shelf hardware. The key features of Swift include (1) extremely low filter upd...
Zhenyu Wu, Mengjun Xie, Haining Wang
ISPASS
2009
IEEE
16 years 25 days ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
ICS
2009
Tsinghua U.
16 years 24 days ago
Towards 100 gbit/s ethernet: multicore-based parallel communication protocol design
Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires ...
Stavros Passas, Kostas Magoutis, Angelos Bilas