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MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 2 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
GRID
2005
Springer
14 years 2 months ago
SERVOGrid complexity computational environments (CCE) integrated performance analysis
In this paper we describe the architecture and initial performance analysis results of the SERVOGrid Complexity Computational Environments (CCE). The CCE architecture is based on ...
Galip Aydin, Mehmet S. Aktas, Geoffrey Fox, Harsha...
ICDCSW
2002
IEEE
14 years 2 months ago
Peer-to-Peer for Collaborative Applications
Peer-to-peer systems recently captured the attention of practitioners and researchers as they provide an attractive alternative to client-server architectures. Peerto-peer enables...
Gianpaolo Cugola, Gian Pietro Picco
CAMP
2005
IEEE
14 years 2 months ago
Speeding-up NCC-Based Template Matching Using Parallel Multimedia Instructions
— This paper describes the mapping of a recently introduced template matching algorithm based on the Normalized Cross Correlation (NCC) on a general purpose processor endowed wit...
Luigi di Stefano, Stefano Mattoccia, Federico Tomb...
IEEEPACT
2000
IEEE
14 years 1 months ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany