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JUCS
2000
120views more  JUCS 2000»
15 years 4 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
CSREAESA
2006
15 years 5 months ago
Integration of an Analysis Tool for Large-Scale Embedded Real-Time Software into a Vehicle Control Platform Development Tool Cha
- We present a software tool for high-level design and analysis of large-scale embedded real-time software, which has been integrated into a vehicle control platform development to...
Xiaofeng Yin, Daniel L. Kiskis, Daniel Mihalik, Ka...
FDL
2007
IEEE
15 years 10 months ago
Time Modeling in MARTE
This article introduces the Time Model subprofile of MARTE, a new OMG UML Profile dedicated to Modeling and Analysis of Real-Time and Embedded systems. After a brief presentatio...
Robert de Simone, Charles André
JSAC
2007
130views more  JSAC 2007»
15 years 4 months ago
Cross-layer QoS Analysis of Opportunistic OFDM-TDMA and OFDMA Networks
Abstract— Performance analysis of multiuser orthogonal frequency division multiplexing (OFDM-TDMA) and orthogonal frequency division multiple access (OFDMA) networks in support o...
Yu-Jung Chang, Feng-Tsun Chien, C. C. Jay Kuo
ICNP
2000
IEEE
15 years 8 months ago
A Topology-Independent Fair Queueing Model in Ad Hoc Wireless Networks
Fair queueing of rate and delay-sensitive packet flows in a shared-medium, multihop wireless network remains largely unaddressed because of the unique design issues such as locat...
Haiyun Luo, Songwu Lu