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CONEXT
2007
ACM
13 years 12 months ago
On the cost of caching locator/ID mappings
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
Luigi Iannone, Olivier Bonaventure
IPPS
2006
IEEE
14 years 2 months ago
A framework to develop symbolic performance models of parallel applications
Performance and workload modeling has numerous uses at every stage of the high-end computing lifecycle: design, integration, procurement, installation and tuning. Despite the trem...
Sadaf R. Alam, Jeffrey S. Vetter
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Constraint-driven bus matrix synthesis for MPSoC
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
JUCS
2006
112views more  JUCS 2006»
13 years 8 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
AES
2005
Springer
137views Cryptology» more  AES 2005»
13 years 7 months ago
Design of a multimedia processor based on metrics computation
Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-...
Nader Ben Amor, Yannick Le Moullec, Jean-Philippe ...