223 search results - page 29 / 45 » Scheduling Memory Constrained Jobs on Distributed Memory Par... |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
DCOSS
2008
Springer
13 years 9 months ago
2008
Springer
Abstract. We propose FIT, a flexible, light-weight and real-time scheduling system for wireless sensor platforms. There are three salient features of FIT. First, its two-tier hiera...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...