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» Scheduling and Module Assignment for Reducing Bist Resources
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GLVLSI
2002
IEEE
98views VLSI» more  GLVLSI 2002»
14 years 12 days ago
Minimizing concurrent test time in SoC's by balancing resource usage
We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each c...
Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
CGO
2004
IEEE
13 years 11 months ago
Probabilistic Predicate-Aware Modulo Scheduling
Predicated execution enables the removal of branches by converting segments of branching code into sequences of conditional operations. An important side effect of this transforma...
Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Da...
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 11 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
ACSD
2010
IEEE
251views Hardware» more  ACSD 2010»
13 years 5 months ago
Modular Interpretation of Heterogeneous Modeling Diagrams into Synchronous Equations Using Static Single Assignment
Abstract--The ANR project SPaCIFY develops a domainspecific programming environment, Synoptic, to engineer embedded software for space applications. Synoptic is an Eclipse-based mo...
Jean-Pierre Talpin, Julien Ouy, Thierry Gautier, L...
MICRO
1997
IEEE
105views Hardware» more  MICRO 1997»
13 years 11 months ago
The Multicluster Architecture: Reducing Cycle Time Through Partitioning
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvon...