540 search results - page 91 / 108 » Scheduling dynamic parallelism on accelerators |
JSSPP
2010
Springer
13 years 6 months ago
2010
Springer
Abstract. In this paper, we address job scheduling in Distributed Computing Infrastructures, that is a loosely coupled network of autonomous acting High Performance Computing syste...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
ICDCSW
2003
IEEE
14 years 1 months ago
2003
IEEE
It is a challenging task to provide Quality of Service (QoS) control for a shared high-speed downlink packet access (HSDPA) wireless channel. In this paper, we first propose a ne...
DSD
2002
IEEE
14 years 1 months ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
ISCA
2002
IEEE
14 years 1 months ago
2002
IEEE
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...