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» Scheduling dynamic parallelism on accelerators
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HPCA
2005
IEEE
14 years 2 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
IPPS
2005
IEEE
14 years 2 months ago
Configuration Steering for a Reconfigurable Superscalar Processor
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...
Brian F. Veale, John K. Antonio, Monte P. Tull
EGC
2005
Springer
14 years 2 months ago
eNANOS Grid Resource Broker
Grid computing has been presented as a way to share geographically and organizationally distributed resources and to perform successfully distributed computation. For achieve this ...
Ivan Rodero, Julita Corbalán, Rosa M. Badia...
HPDC
2002
IEEE
14 years 1 months ago
A Decentralized, Adaptive Replica Location Mechanism
We describe a decentralized, adaptive mechanism for replica location in wide-area distributed systems. Unlike traditional, hierarchical (e.g, DNS) and more recent (e.g., CAN, Chor...
Matei Ripeanu, Ian T. Foster
PDP
2010
IEEE
14 years 23 days ago
hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
François Broquedis, Jérôme Cle...