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ICCAD
2001
IEEE
91views Hardware» more  ICCAD 2001»
14 years 4 months ago
A System for Synthesizing Optimized FPGA Hardware from MATLAB
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
Malay Haldar, Anshuman Nayak, Alok N. Choudhary, P...
RTAS
2008
IEEE
14 years 2 months ago
Throttling On-Disk Schedulers to Meet Soft-Real-Time Requirements
To achieve better throughput, many hard drive manufacturers use internal queues and scheduling to take advantage of vendor-specific characteristics and knowledge. While this tren...
Mark J. Stanovich, Theodore P. Baker, An-I Andy Wa...
COOPIS
2002
IEEE
14 years 23 days ago
Empirical Differences between COTS Middleware Scheduling Strategies
The proportion of complex distributed real-time embedded (DRE) systems made up of commercial-off-the-shelf (COTS) hardware and software is increasing significantly in response to...
Christopher D. Gill, Fred Kuhns, Douglas C. Schmid...
SOCO
2007
Springer
14 years 1 months ago
Synthesizing Communication Middleware from Explicit Connectors in Component Based Distributed Architectures
In component based software engineering, an application is build by composing trusted and reusable units of execution, the components. A composition is formed by connecting the com...
Dietmar Schreiner, Karl M. Göschka
EMSOFT
2006
Springer
13 years 11 months ago
An analysis framework for network-code programs
Distributed real-time systems require a predictable and verifiable mechanism to control the communication medium. Current real-time communication protocols are typically independe...
Madhukar Anand, Sebastian Fischmeister, Insup Lee