Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edw...
— This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by...
The Earliest Deadline First scheduling algorithm (EDF) is known to not be optimal under global scheduling on multiprocessor platforms. Results have been obtained that bound the ma...
Jeremy P. Erickson, UmaMaheswari Devi, Sanjoy K. B...
Abstract Intelligent calendar assistants have many years ago attracted researchers from the areas of scheduling, machine learning and human computer interaction. However, all effor...
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...