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ASPDAC
2005
ACM
146views Hardware» more  ASPDAC 2005»
13 years 11 months ago
High-level synthesis for DSP applications using heterogeneous functional units
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edw...
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
13 years 11 months ago
On multiple-voltage high-level synthesis using algorithmic transformations
— This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by...
Hsueh-Chih Yang, Lan-Rong Dung
ECRTS
2010
IEEE
13 years 9 months ago
Improved Tardiness Bounds for Global EDF
The Earliest Deadline First scheduling algorithm (EDF) is known to not be optimal under global scheduling on multiprocessor platforms. Results have been obtained that bound the ma...
Jeremy P. Erickson, UmaMaheswari Devi, Sanjoy K. B...
IFIP12
2009
13 years 6 months ago
Defining a Task's Temporal Domain for Intelligent Calendar Applications
Abstract Intelligent calendar assistants have many years ago attracted researchers from the areas of scheduling, machine learning and human computer interaction. However, all effor...
Anastasios Alexiadis, Ioannis Refanidis
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
11 years 11 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek