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CAV
2010
Springer
172views Hardware» more  CAV 2010»
14 years 1 months ago
Symbolic Bounded Synthesis
Abstract. Synthesis of finite state systems from full linear time temporal logic (LTL) specifications is gaining more and more attention as several recent achievements have signi...
Rüdiger Ehlers
IJCSS
2007
133views more  IJCSS 2007»
13 years 10 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja
CORR
2010
Springer
98views Education» more  CORR 2010»
13 years 10 months ago
Extended Computation Tree Logic
We introduce a generic extension of the popular branching-time logic CTL which refines the temporal until and release operators with formal languages. For instance, a language may ...
Roland Axelsson, Matthew Hague, Stephan Kreutzer, ...
WCE
2007
13 years 11 months ago
Avoiding Hazards for Speed-Independent Logic Design
- In the speed-independent logic, the hazards caused by input inverters are identified. The known methods of the elimination of such hazards are based on avoiding input inverters. ...
Igor Lemberski
ICALP
2005
Springer
14 years 3 months ago
Probabilistic Polynomial-Time Semantics for a Protocol Security Logic
Abstract. We describe a cryptographically sound formal logic for proving protocol security properties without explicitly reasoning about probability, asymptotic complexity, or the ...
Anupam Datta, Ante Derek, John C. Mitchell, Vitaly...