We consider a class of component-based software models with interaction style of buffered asynchronous message passing between components with ports, represented by UML-RT. After ...
Abstract. As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call...
Josep Carmona, Jordi Cortadella, Victor Khomenko, ...
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
An approach for stuck-at-i and delay-fault testing of redundant circuits without modifying the logic is proposed. The only requirement is the ability to control both phases of eac...
Luciano Lavagno, Antonio Lioy, Michael Kishinevsky
This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short co...