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LCTRTS
2007
Springer
14 years 4 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
MIDDLEWARE
2007
Springer
14 years 4 months ago
CAESAR: middleware for complex service-oriented peer-to-peer applications
Recent research advances in Peer-to-Peer (P2P) computing have enabled the P2P paradigm to be used for developing complex applications beyond file sharing and data storage. These ...
Lipo Chan, Shanika Karunasekera, Aaron Harwood, Eg...
CODES
2006
IEEE
14 years 4 months ago
Multi-processor system design with ESPAM
For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by emb...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
IPPS
2006
IEEE
14 years 4 months ago
Compiler assisted dynamic management of registers for network processors
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
R. Collins, Fernando Alegre, Xiaotong Zhuang, Sant...
ISPASS
2006
IEEE
14 years 4 months ago
Considering all starting points for simultaneous multithreading simulation
Commercial processors have support for Simultaneous Multithreading (SMT), yet little work has been done to provide representative simulation results for SMT. Given a workload, cur...
Michael Van Biesbrouck, Lieven Eeckhout, Brad Cald...
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