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CLUSTER
2008
IEEE
14 years 3 months ago
A trace-driven emulation framework to predict scalability of large clusters in presence of OS Jitter
—Various studies have pointed out the debilitating effects of OS Jitter on the performance of parallel applications on large clusters such as the ASCI Purple and the Mare Nostrum...
Pradipta De, Ravi Kothari, Vijay Mann
HPCC
2010
Springer
13 years 6 months ago
Implementation and Evaluation of a NAT-Gateway for the General Internet Signaling Transport Protocol
The IETF's Next Steps in Signaling (NSIS) framework provides an up-to-date signaling protocol suite that can be used to dynamically install, maintain, and manipulate state in ...
Roland Bless, Martin Röhricht
HPCA
2009
IEEE
14 years 9 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
PC
2007
161views Management» more  PC 2007»
13 years 8 months ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...
IPPS
2003
IEEE
14 years 1 months ago
Targeting Tiled Architectures in Design Exploration
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...