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FDTC
2010
Springer
118views Cryptology» more  FDTC 2010»
13 years 5 months ago
Low Cost Built in Self Test for Public Key Crypto Cores
The testability of the cryptographic cores brings in an extra dimension to the process of digital circuits testing
Dusko Karaklajic, Miroslav Knezevic, Ingrid Verbau...
CORR
2010
Springer
95views Education» more  CORR 2010»
13 years 5 months ago
When are feedforward microcircuits well-modeled by maximum entropy methods?
Describing the collective activity of neural populations is a daunting task: the number of possible patterns grows exponentially with the number of cells, resulting in practically...
Andrea K. Barreiro, Julijana Gjorgjieva, Fred Riek...
VTS
2002
IEEE
107views Hardware» more  VTS 2002»
14 years 14 days ago
Testing High-Speed SoCs Using Low-Speed ATEs
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate...
Mehrdad Nourani, James Chin
IJON
2007
118views more  IJON 2007»
13 years 7 months ago
Low power CMOS electronic central pattern generator design for a biomimetic underwater robot
— This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...
Young-Jun Lee, Jihyun Lee, Kyung Ki Kim, Yong-Bin ...
DATE
2005
IEEE
127views Hardware» more  DATE 2005»
14 years 1 months ago
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...