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GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
13 years 9 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
VLSISP
2008
173views more  VLSISP 2008»
13 years 7 months ago
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence...
Yedidya Hilewitz, Ruby B. Lee
DT
2000
162views more  DT 2000»
13 years 7 months ago
RT-Level ITC'99 Benchmarks and First ATPG Results
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
JOCN
2010
71views more  JOCN 2010»
13 years 6 months ago
Mechanisms and Dynamics of Cortical Motor Inhibition in the Stop-signal Paradigm: A TMS Study
■ The ability to stop ongoing motor responses in a splitsecond is a vital element of human cognitive control and flexibility that relies in large part on prefrontal cortex. We u...
Wery P. M. van den Wildenberg, Borís Burle,...
KDD
2006
ACM
253views Data Mining» more  KDD 2006»
14 years 8 months ago
Adaptive Website Design Using Caching Algorithms
Visitors enter a website through a variety of means, including web searches, links from other sites, and personal bookmarks. In some cases the first page loaded satisfies the visi...
Justin Brickell, Inderjit S. Dhillon, Dharmendra S...