605 search results - page 24 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
FPL
2007
Springer
13 years 11 months ago
2007
Springer
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
ISPAN
2000
IEEE
13 years 11 months ago
2000
IEEE
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
ASPLOS
2004
ACM
14 years 25 days ago
2004
ACM
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
WMPI
2004
ACM
14 years 24 days ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...