605 search results - page 29 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
DAC
2001
ACM
14 years 8 months ago
2001
ACM
A software energy estimation methodology is presented that avoids explicit characterization of instruction energy consumption and predicts energy consumption to within 3% accuracy...
ASM
2005
ASM
13 years 9 months ago
2005
ASM
Abstract. This paper provides a modular high-level design of the Common Language Runtime (CLR) architecture. Our design is given in terms act State Machines (ASMs) and takes the fo...
HIPEAC
2007
Springer
14 years 1 months ago
2007
Springer
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. T...
SBACPAD
2009
IEEE
14 years 2 months ago
2009
IEEE
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
CSE
2008
IEEE
13 years 9 months ago
2008
IEEE
A well-known challenge during processor design is to obtain best possible results for a typical target application domain by combining flexibility and computational performance. A...