605 search results - page 96 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
DAC
2004
ACM
14 years 9 months ago
2004
ACM
This paper presents a set of comprehensive techniques for the intratask voltage scheduling problem to reduce energy consumption in hard real-time tasks of embedded systems. Based ...
DSVIS
2003
Springer
14 years 1 months ago
2003
Springer
CAD systems have yet to become usable at the early stages of product ideation, where precise shape definitions and sometimes even design intentions are not fully developed. To over...
RTSS
1998
IEEE
14 years 21 days ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
CODES
2009
IEEE
14 years 3 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
Performance projections of High Performance Computing (HPC) applications onto various hardware platforms are important for hardware vendors and HPC users. The projections aid hard...